Digital Logic Design
Flip-Flop Characteristic & Excitation Tables
SR, JK, D, and T flip-flops as tables: the characteristic table (what Q⁺ will be) and the excitation table (what inputs force a wanted transition), with a live next-state evaluation.
About this calculator
Two tables carry everything a designer needs to know about a flip-flop, and they answer opposite questions. The CHARACTERISTIC table runs forward — given the present state Q and the inputs, what is the next state Q⁺? — and compresses into the characteristic equation (Q⁺ = JQ̄ + K̄Q for the JK, Q⁺ = D for the D, and so on). The EXCITATION table runs backward — given a transition you WANT, from Q to Q⁺, what must the inputs be? — and is the table that sequential-circuit synthesis actually consumes: counter and state-machine design is excitation-table lookups feeding a K-map.
This tool shows both tables for all four classical types, plus a live evaluation: set the present state and inputs and read Q⁺, with the corresponding characteristic-table row highlighted. The personalities are stated plainly — SR with its forbidden S = R = 1 combination (shown as forbidden, not hidden), JK repurposing that combination as toggle, D as the pure data-follower that modern synchronous design standardized on, T as the natural divider-by-two.
The excitation don't-cares are the useful subtlety: to go 0 → 1 with a JK, J must be 1 but K can be anything — and those X entries are exactly the don't-cares that make the K-maps of a state-machine design collapse. The tables here are the same ones that feed the Karnaugh solver two clicks away.
Deliberately combinational-only this pass: these are the timeless truth-table facts of the devices. Clocking, edges, setup and hold belong to the planned sequential and timing batches.
Design notes & common mistakes
- Characteristic tables answer 'what will happen'; excitation tables answer 'what must I apply'. Synthesis uses the second — reaching for the first is the standard homework wrong-turn.
- The JK's many excitation don't-cares (two X's across the four transitions) are why JK-based counters often minimize smaller than D-based ones — and why D still wins in practice: simpler timing and no gated feedback.
- The SR forbidden state is not academic: release S = R = 1 simultaneously and the device races. Designs that can't exclude it must use JK or D instead.
- These tables say nothing about WHEN the transition happens — clock edge, setup, and hold are separate (deferred) contracts layered on top.
Assumptions
- Ideal storage elements described at the level of their defining tables; the active clock event is implicit in Q⁺.
- Positive logic; single flip-flop (registers and counters are the planned sequential batch).
When to use this calculator
Appropriate for
- Looking up SR/JK/D/T characteristic and excitation tables and evaluating a next state
- Getting the excitation don't-cares that feed a state-machine or counter design's K-maps
- Teaching the four flip-flop types and their defining behaviors
Not suitable for
- Timing behavior — clock edges, setup/hold, and metastability are out of scope (see the planned timing batch)
- Multi-bit registers, shift registers, and counters (planned sequential batch), which build on these tables
- Asynchronous preset/clear behavior, which overrides these synchronous tables
What this calculator does not cover
- Combinational tables only: no clock modeling, no edge vs level triggering, no setup/hold or metastability — those are the planned timing-analysis batch.
- Single-bit devices; multi-bit registers, shift registers, and counters are the planned sequential-logic batch (they consume exactly these excitation tables).
- Asynchronous preset/clear pins are not modeled — they override these tables by construction.
- As with every calculator on this site: results are preliminary and educational, are not verified for any specific installation, and must be reviewed against the applicable code edition and stamped by a licensed Professional Engineer before real-world use.
Frequently asked questions
What is the difference between the characteristic and excitation tables?
Direction. The characteristic table predicts: given Q and the inputs, here is Q⁺. The excitation table prescribes: to force a chosen Q → Q⁺ transition, apply these inputs. Analysis uses the first; design (counters, state machines) uses the second.
Why is S = R = 1 forbidden but J = K = 1 fine?
In the SR latch both outputs are driven low simultaneously, and the final state after release is a race — indeterminate. The JK adds feedback that turns that same input pair into a well-defined TOGGLE, which is precisely the JK's reason to exist.
Why does modern design use D flip-flops almost exclusively?
Q⁺ = D is the simplest possible contract: no input coupling, no forbidden states, and it matches how synthesis tools think (compute the next state combinationally, register it). JK's excitation don't-cares saved gates in the SSI era; today the timing simplicity of D wins.
References
- Mano, M. M. & Ciletti, M., Digital Design, 6th ed., Ch. 5 (flip-flops, characteristic and excitation tables)
- Roth, C. H. & Kinney, L., Fundamentals of Logic Design, 7th ed. (sequential building blocks)
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