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Digital Logic Design

Combinational logic and number systems on a provably-correct engine: an interactive Karnaugh map solver (2–5 variables, don't-cares, exact Quine–McCluskey groupings), Boolean expression simplification to verified minimal SOP and POS, truth-table generation with editable cells, SOP↔POS conversion, the standard gates with their distinctive-shape symbols, base/BCD/Gray/two's-complement/ASCII conversion with worked steps, and the flip-flop characteristic and excitation tables. Every minimized expression is checked back against its source truth table before it is shown — a simplification here always comes with its proof of equivalence. Sequential logic and timing analysis are planned follow-on batches.