Digital Logic Design
Logic Gate Evaluator
Every standard gate — AND, OR, NOT, NAND, NOR, XOR, XNOR — with its distinctive-shape symbol, live input toggling, full truth table, and what each gate is actually for.
About this calculator
Seven gates carry all of digital logic, and knowing them cold — symbol, table, and personality — is the alphabet the rest of the subject is written in. This evaluator puts one gate at a time on the bench: pick the type, set the inputs, and read the output off the rendered distinctive-shape symbol (ANSI/IEEE Std 91 shapes — the D-shaped AND, the shield-shaped OR, the inverter bubble that turns them into NAND and NOR) with asserted wires lit in the signal accent.
The full truth table sits beside the symbol with the current input row highlighted, so the single evaluation you set and the complete behavior stay connected. The descriptions carry the working engineer's shorthand: NAND and NOR are the functionally complete pair (either one alone can build everything — the reason NAND-NAND structures dominate), XOR is the difference detector at the heart of adders and parity, XNOR the equality comparator.
It is deliberately the simplest tool in the toolkit — level 1, one gate, no minimization — because it is the reference the others lean on: when a K-map result says F = AB + C̄, this page is where each of those symbols has a face, a table, and a reason to exist.
Design notes & common mistakes
- NAND and NOR are each functionally complete: with enough of either, every Boolean function is buildable. CMOS makes them cheaper than AND/OR (which are NAND/NOR plus an inverter), which is why synthesized logic is NAND/NOR-rich.
- An XOR is not 'OR but stricter' — it is addition modulo 2. That reading makes half-adders, parity trees, and Gray-code converters obvious instead of mysterious.
- The inverter bubble is notation with algebra inside: a bubble on an input or output is a De Morgan transformation waiting to be pushed through the gate.
- Real gates add propagation delay and drive limits (fan-out) — behavior this logical view deliberately omits; see the planned timing-analysis batch.
Assumptions
- Ideal logical behavior: no propagation delay, no loading, no noise margins — the Boolean abstraction.
- Two-input forms of the multi-input gates (the n-input generalizations follow the same definitions).
When to use this calculator
Appropriate for
- Looking up any standard gate's truth table, symbol, and behavior at chosen inputs
- Confirming the output of a single gate, or recalling why NAND/NOR are universal
- Teaching the standard gates as the building blocks of logic
Not suitable for
- Cascaded gate networks — enter those as a Boolean expression in the truth-table or simplifier tools
- Electrical behavior: propagation delay, fan-out, and drive strength are out of scope (see the planned timing batch)
- Active-low or mixed-logic conventions beyond the positive-logic tables shown
What this calculator does not cover
- Single gates and their tables only — cascaded networks belong to the expression tools, where any gate combination can be typed as an expression.
- No electrical characteristics: delay, fan-out, and drive strength are the planned timing-analysis batch's domain.
- Positive-logic convention only; active-low signal naming is a labeling discipline layered on top of these same tables.
- As with every calculator on this site: results are preliminary and educational, are not verified for any specific installation, and must be reviewed against the applicable code edition and stamped by a licensed Professional Engineer before real-world use.
Frequently asked questions
Why are NAND and NOR called universal gates?
Because either one alone is functionally complete: NOT is a NAND with joined inputs, AND is NAND + NOT, OR follows by De Morgan — and symmetrically for NOR. Combined with CMOS making them the cheapest gates, that's why real chips are full of them.
What's the practical difference between XOR and OR?
OR is true when at least one input is 1; XOR when the inputs DIFFER (exactly one is 1, for two inputs). XOR is addition modulo 2 — the sum bit of a half adder, the core of parity generation and checking, and the binary↔Gray code converter.
What does the small circle on NAND, NOR, and NOT mean?
The inversion bubble: the gate's output (or an input, where drawn) is complemented. It is also a reasoning tool — 'pushing bubbles' through a diagram is De Morgan's theorem performed graphically.
References
- Mano, M. M. & Ciletti, M., Digital Design, 6th ed., Ch. 2 (basic gates, universality of NAND/NOR)
- IEEE Std 91/91a (graphic symbols for logic functions — distinctive shapes)
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